With the demand for sophisticated electronic instruments in recent years, there have been developed high-density integration and high-density mounting of electronic components. Because of this, printed wiring boards designed for high-density mounting and for use in such instruments are increasingly downsized and provided with higher density. To meet the demand for a higher-density printed wiring board, a multilayer printed wiring board produced by the build-up method is employed in many cases (see Patent Literature 1, for example).
Normally, the multilayer printed wiring board produced by the build-up method is formed by laminating conductor circuit layers and insulation layers comprising a resin composition and having a thickness of 100 μm or less, and molding the same. As the method for connecting between conductor circuit layers, there may be mentioned via hole formation by a laser method, photolithography method or the like, instead of conventional drilling. These methods realize higher-density by providing small via holes freely, and for each of various build-up methods corresponding to each method, a resin sheet provided with a substrate is proposed.
Furthermore, to obtain higher density, it is necessary to form a fine circuit. As a technique to achieve it, a semi-additive method is widely known. The semi-additive method is a method for forming a conductive circuit on an insulation layer in such a manner that, following surface roughening of an insulation layer, electroless plating is performed thereon so as to function as a base coat, and after a non-circuit forming area is protected with a plating resist, copper is deposited on a circuit forming area by electroplating, followed by removal of the resist and soft etching.
Studies are provided into the production of a multilayer printed wiring board by the semi-additive method; however, there are problems such as a decrease in plating adhesion which occurs during production process, a decrease in heat resistance or moisture resistance reliability attributed to the type of the insulation resin layer used.
For example, in the case of using a phenoxy resin having a bisphenol acetophenone structure for an insulation layer (e.g., Patent Literature 2) or in the case of using a cyanate ester resin for an insulation layer (Patent Literature 3), there is a problem with plating adhesion, so that such insulation layers are not applicable to the semi additive method.
In the case of using an insulation resin layer comprising an epoxy resin, a specific phenolic curing agent, a phenoxy resin and rubber particles (e.g., Patent Literature 4), relatively good plating adhesion can be obtained; however, heat resistance or moisture resistance reliability is not enough. Because of this, application of such an insulation resin layer into multilayer printed wiring boards that are required to have high reliability, is difficult.
Currently, in the case of using a resin sheet in a multilayer printed wiring board, in order to minimize warpage of the board, there are studied decreasing the expansion characteristics of an insulation resin layer, (Patent Literature 5), surface smoothness (Patent Literature 6), a low surface roughness (Ra) of 0.4 μm or less which makes the surface of an insulation resin layer resistant to fine wiring process, and improvement of plating adhesion (Patent Literatures 4, 7, 8, 9 and 10).
However, none of them can solve all of the problems. In the future, especially since the width of circuit conductors and the width of the gap between circuit conductors will be small, there would be a serious problem with insulation reliability of fine circuits. Also disclosed is a case of using a prepreg in an insulation resin layer to obtain low thermal expansion characteristics (Patent Literatures 9 and 10); however, it cannot satisfy low thermal expansion characteristics, formation of fine wiring and insulation reliability of fine circuits.
Patent Literature 1: Japanese Patent Application Laid-Open (JP-A) No. H07-106767
Patent Literature 2: JP-A No. 2003-342350
Patent Literature 3: JP-A No. H09-100393
Patent Literature 4: JP-A No. 2007-254709
Patent Literature 5: Domestic Re-publication of PCT International Publication for Patent Application No. 03/099952
Patent Literature 6: JP-A No. 2005-240019
Patent Literature 7: JP-A No. 2005-244150
Patent Literature 8: JP-A No. 2007-254710
Patent Literature 9: JP-A No. 2008-007575
Patent Literature 10: JP-A No, 2008-074929